Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, or a Cu alloy since Cu-based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al,-based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
In current semiconductor interconnect structures, time-dependent-dielectric-breakdown (TDDB) has been identified as one of the major reliability concerns for future interconnect structures that include Cu-based metallurgy and low k dielectric materials. By “TDDB” it is meant, that overtime the dielectric material of the interconnect structure (i.e., the interconnect dielectric) begins to fail. The failure of the interconnect dielectric material may be caused by intrinsic means or by defects that are formed on the surface of the interconnect dielectric material during the course of preparing the interconnect structure.
Leakage of metallic ions, particularly Cu ions, along the interconnect dielectric surface has been identified as the major intrinsic failure mechanism that attributes to TDDB. FIG. 1A is a prior art interconnect structure 10 which illustrates this intrinsic leakage phenomenon. Specifically, the prior art interconnect structure includes a dielectric material 12 having a Cu feature 14 embedded therein. The Cu feature 14 is typically separated from the dielectric material 12 by a diffusion barrier 16. A dielectric capping layer 18 is present on the surface of the dielectric material 12, the diffusion barrier 16 and the Cu feature 14. In FIG. 1A, the arrows designate the leakage (diffusion) of Cu ions from the conductive feature 14 which occurs along the upper surface of the interconnect structure as shown. Overtime, this leakage of Cu ions results in TDDB as well as failure of the devices within the interconnect structure.
Another contributor to TDDB, which is illustrated in FIG. 1B, is defect related. Specifically, FIG. 1B is another prior art interconnect structure 10′ including the components as shown in FIG. 1A in which Cu residues (e.g., defects) 20 are present at the interface between the upper surface of the dielectric material 12 and the dielectric capping layer 18. The Cu residues 20 are formed during the formation of the Cu features 14 (i.e., deposition and planarization of Cu within an opening formed into the dielectric material 12). Post planarization Cu residues, which provide defects at the surface of the dielectric material, are one of the root causes of time-dependent-dielectric-breakdown (TDDB) failure.
It is noted that although Cu is specifically mentioned with respect to the prior art interconnect structures mentioned above, the above leakage and defect problems occur (although at different rates and extents) with other types of conductive metals such as, for example Al and W.
It is further noted that in each of the prior art structures mentioned above, a dielectric capping layer 18 is formed upon the interconnect level including at least the dielectric material 12 and the Cu feature 14. Typically, the dielectric capping layer 18 is formed by first subjecting the exposed surface of the interconnect level including the dielectric material 12 and the Cu feature 14 to a preclean step. In current interconnect processing, such a preclean includes a NH3 plasma treatment. Following the preclean step, the dielectric capping layer 18 is then deposited. It is observed that the plasma preclean and the deposition typically occur in-situ within the same processing tool.
Leakage measurements have shown that no degradation from leakage current occurs after deposition of the dielectric capping layer 18. Although no degradation from leakage current was observed after deposition of the dielectric capping layer, leakage measurements performed after the plasma preclean step, but prior to dielectric capping layer deposition, show that leakage is occurring. While not entirely known, this degradation, which occurs after the NH3 plasma pretreatment, but prior to deposition of the dielectric capping layer, may be a TDDB related issue.
In view of the leakage problem illustrated in FIG. 1A, and the residues problem illustrated in FIG. 1B, there is a continued need for providing an interconnect structure in which metallic leakage, particularly, Cu ion diffusion, and metallic residues, particularly Cu residues, can both be reduced or completely eliminated from an interconnect structure.